1. Field
The following description relates to an apparatus and a method for processing an invalid operation in a prologue and/or an epilogue of a software pipelined loop.
2. Description of Related Art
Software pipelining is a technique used to divide software into stages and execute operations in a pipeline manner, thereby improve the processing performance. However, because a coarse-grained reconfigurable architecture (CGRA) processor schedules a program by exploiting modulo scheduling, an invalid operation may be included in a prologue and/or an epilogue of a loop.
Generally, the CGRA processor uses predicate information to guard an invalid operation in a prologue and/or an epilogue of a loop from changing a program status. “Guarding” refers to pre-processing to control the execution of an invalid operation, and more specifically, to control the invalid operation not to be written in a register file even when a functional unit actually executes the invalid operation. To use the predicate information, routing information of the CGRA for the predicate is required. A CGRA compiler is in charge of the computation of the predicate and the routing, which may cause the scheduling procedure of the compiler to be complicated. In the case of a kernel of a complex loop, the computation of the predicate and the routing may lead to the failure of scheduling.